* CPU IF (9bit data bus)
- 2 cycle transfer through 9bit data bus
- assignment
DB17,DB16,DB15,DB14,DB13,DB12,DB11,DB10,DB9
R5, R4, R3, R2, R1, R0, G5, G4, G3
G2, G1, G0, B5, B4, B3, B2, B1, B0
- IM3-0(system interface selection)
IM3 IM2 IM1 IM0
1010 -> 80-system 18bit interface
0010 -> 80-system 16bit interface
0011 -> 80-system 8bit interface
1011 -> 80-system 9bit interface
- registers
IR : 16bit index register
WDR : 18bit write-data register
RDR : 18bit read-data register
- register selection(parallel interface)
WRB RDB RS
010 -> Write index of IR
100 -> Setting disabled
011 -> write to a control register and internal GRAM via WDR
101 -> Read from the internal GRAM via the RDR
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