#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
#include "binary.h"
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
enum {
Alt0_BulkIN = 0,
Alt1_IsocTripleIN,
Alt2_IsocIN
};
enum {
Full_Alt0_BulkIN = 0,
Full_Alt1_IsocIN
};
BYTE Configuration; // Current configuration
BYTE AlternateSetting = Alt0_BulkIN; // Alternate settings
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// int i,j;
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1 | bmCLKOE);
SYNCDELAY;
// when IFCFG[1:0] = 0b11,
// FIFOADR[1:0], PKTEND, and SLOE are automatically configured
// for PORTA
// PA.3(PORTACFG.3=0, WU2EN=0)
// PA.2(PORTACFG.2=0)
// PA.1(PORTACFG.1=0)
// PA.0(PORTACFG.0=0)
PORTACFG = 0;
WAKEUPCS &= ~0x02; // WU2EN=0
OEA = 0x08b; // Input FIFOADR[0:1], PKTEND, OUTPUT(PA0, PA1)
IOA = 0;
PA0 = 0;
PA1 = 0;
// When IFCFG.1 = 1
// PB[0:7] is configured as FD[0:7]
OEB = 0; // Input as FD[0:7]
IOB = 0;
// When IFCFG.1 = 1 and any WORDWIDE bit = 1
// PD[0:7] is configured as FD[8:15]
OED = 0; // Input as FD[8:15]
IOD = 0;
PORTECFG = 0x03; // needs to be set GSTATE to zero
OEE = 0x3; // IFCLK, CLKOUT
IOE = 0;
/* 1. Configure bits IFCONFIG[7:4] to define the behavior of the interface clock. */
// IFCONFIG
// bit7 : IFCLKSRC(0 -> exernal clock, 1 -> internal clock)
// bit6 : 3048MHZ(0 -> 30Mhz, 1 -> 48Mhz)
// bit5 : IFCLKOE(0 -> disable, 1-> enable internal clock output)
// bit4 : IFCLKPOL(invert external or internal clock)
// bit3 : ASYNC(0 -> synchronous, 1 -> asynchronous)
// bit2 : GSTATE(0 -> disable GSTATE, 1-> enable GSTATE)
// bit1 : IFCFG[1:0] (0b00: ports, 0b01: reserved, 0b10: GPIF, 0b11: Slave fifo)
// bit0 :
IFCONFIG = b01010100; // ext, 48Mhz, disable OE, invert, synchronous, enable GSTATE, ports
/* 2. Set bits IFCFG1:0=11. */
IFCONFIG |= b00000011;
SYNCDELAY;
/* 3. Set REVCTL.0 and REVCTL.1 to 1. */
REVCTL = 0x03;
SYNCDELAY;
/* 4. Configure EPxCFG. */
// Default interface uses endpoint 2, zero the valid bit on all others
// Just using endpoint 2, zero the valid bit on all others
EP1OUTCFG = 0xA0; //bmVALID | bmBULK;
SYNCDELAY;
EP1INCFG = 0xA0; //bmVALID | bmBULK;
SYNCDELAY;
// EPxCFG
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; //EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
EP4CFG = (EP4CFG & 0x7F); //non-valid
SYNCDELAY;
EP6CFG = (EP6CFG & 0x7F); //non-valid
SYNCDELAY;
EP8CFG = (EP8CFG & 0x7F); //non-valid
SYNCDELAY;
// EPxFIFOCFG
// bit7 : reserved
// bit6 : INFM1(IN Full Minus One)
// bit5 : OEP2(OUT Empty Plus One)
// bit4 : AUTOOUT
// bit3 : AUTOIN
// bit2 : ZEROLENIN(Enable Zero-length IN Packets)
// bit1 : reserved
// bit0 : WORDWIDE(Select Byte/Word FIFOs on PORTB/D Pins)
//EP2FIFOCFG = 0x01;
EP2FIFOCFG = 0x00; // 8bit FD
SYNCDELAY;
EP4FIFOCFG = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x00;
SYNCDELAY;
EP8FIFOCFG = 0x00;
SYNCDELAY;
/* 5. Reset the FIFOs. */
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY; //
/* 6. Set bit EPxFIFOCFG.3=1. */
EP2FIFOCFG |= 0x08; // AUTOIN
/* 7. Set the size via the EPxAUTOINLENH:L registers. */
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
// We want to get SOF interrupts
USBIE |= bmSOF;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
if (PA0) PA0 = 0; // de-assert reset
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
BYTE updateDisplay = TRUE;
AlternateSetting = SETUPDAT[2];
// ...FX2 in high speed mode
if (EZUSB_HIGHSPEED()) {
// Change configuration based upon the Alt. Interface selected
switch (AlternateSetting) {
case Alt0_BulkIN:
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
break;
case Alt1_IsocTripleIN:
// Only using endpoint 2, zero the valid bit on all others
EP2CFG = 0xD8; //bmVALID | bmIN | bmISOC | bm1024 | bmQUAD // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1024);
SYNCDELAY;
EP2AUTOINLENL = LSB(1024);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x03;
break;
case Alt2_IsocIN:
EP2CFG = 0xD8; //bmVALID | bmIN | bmISOC | bm1024 | bmQUAD // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1024);
SYNCDELAY;
EP2AUTOINLENL = LSB(1024);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
break;
}
} else {
// Change configuration based upon the Alt. Interface selected
switch (AlternateSetting) {
case Full_Alt0_BulkIN:
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
break;
case Full_Alt1_IsocIN:
EP2CFG = 0xD8; // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1023);
SYNCDELAY;
EP2AUTOINLENL = LSB(1023);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
break;
}
}
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
#include "commands.h"
#define bRequestType SETUPDAT[0]
#define bRequest SETUPDAT[1]
#define wValueL SETUPDAT[2]
#define wValueH SETUPDAT[3]
#define wIndexL SETUPDAT[4]
#define wIndexH SETUPDAT[5]
#define wLengthL SETUPDAT[6]
#define wLengthH SETUPDAT[7]
BOOL DR_VendorCmnd(void)
{
// BYTE xdata tmp[2];
switch (bRequest) {
case VRQ_GET_STATUS:
EP0BUF[0] = IFCONFIG;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
case VRQ_SEND_RESET: PA0 = 1; break;
case VRQ_I2C_WRITE:
// tmp[0] = wIndexL; tmp[1] = wValueL;
// if (EZUSB_WriteI2C(CAM_I2C_ID, 2, &(tmp[0])) != I2C_OK) return TRUE;
break;
case VRQ_I2C_READ:
//IOA ^= 0x04;
//tmp[0] = wIndexL; //i2c_id;
// if (EZUSB_WriteI2C(CAM_I2C_ID, 1, &wIndexL) != I2C_OK) return TRUE;
// EZUSB_WaitForEEPROMWrite(CAM_I2C_ID);
// if (EZUSB_ReadI2C(CAM_I2C_ID, 1, EP1INBUF) != I2C_OK) return TRUE;
//EP1INBUF[0] = tmp[0]; SYNCDELAY;
// EP1INBC = 1; SYNCDELAY; // arm EP6IN
/*
// echo
EP0BUF[0] = tmp[0];
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
*/
break;
#if 0
// case VRQ_SEND_GRAB: PA0 = 0; TR0 = 1; break;
// case VRQ_SEND_START: PA0 = 0; break;
// case VRQ_SEND_STOP: PA0 = 1; break;
case VRQ_SET_CAM:
// if (system_status == NORMAL_STATUS) system_status = SLFIFO_INIT;
// else SEND_START();
break;
case VRQ_RESET_CAM:
// if (system_status != NORMAL_STATUS) system_status = NORMAL_INIT;
break;
#endif
default: return TRUE;
}
return FALSE;
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures(void) interrupt 0
{
if (EZUSB_HIGHSPEED()) {
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
} else {
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp(void) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUSP;
}
void ISR_Highspeed(void) interrupt 0
{
if (EZUSB_HIGHSPEED()) {
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x03;
} else {
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
// ISR_Ep2inout is called on every OUT packet receieved.
// We don't do anything with the data. We just indicate we are done with the buffer.
void ISR_Ep2inout(void) interrupt 0
{
// Perform USB activity based upon the Alt. Interface selected
/*
switch (AlternateSetting)
{
case Alt1_BulkOUT:
case Alt4_IsocOUT:
// check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP2EMPTY))
{
EP2BCL = 0x80; // re(arm) EP2OUT
}
break;
case Alt2_BulkINOUT:
case Alt6_IsocINOUT:
// check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP6EMPTY))
{
EP6BCL = 0x80; // re(arm) EP6OUT
}
break;
}
*/
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
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