2010년 4월 26일 월요일
2010년 4월 22일 목요일
내가 원하는 핸드폰(모바일폰, 셀폰 ... ???)
- 쿼티
세종대왕님이 한글을 잘만들어서 숫자위주로 구성된 버튼으로 충분히 수용가능
- 터치
- 폴터, 슬라이드
- 결국, 바타입의 버튼 스타일의 한손에 잡히는 폰.. 이게 내가 원하는 폰
- 중국에서는 나온다. 저가 형으로 이제서야 우리나라에서는 여기저기 난자 된 상태로 하나씩 하나씩 찔끔찔끔 개선되면서 나오다가 트랜드에 뒤쳐져 아예 사라졌지만 중국에서는 제대로된 상태로 그냥 나오고 있다.
2010년 4월 15일 목요일
Incredible Korea-Traditional Song
조공례 - 대지의 창
CHO GONG RAE - Linernotes
Cho Gong Rae is a celestial nymph, down on the grassland to sing her song. Her singing is a gentle, beautiful breeze, clear and vivid. Her singing voice creates a cool, refreshing steam in the air. Her everclear high note is filled with light but righ vitality, just like the chirping of the birds and brand new buds coming out in the early spring.
The voice of Cho Gong Rae has some kind of wildness in it, but It is not in the vein of any obvious primitive sensibility. It is something that one could feel the warmth and grace of wild nature. Her graceful, smooth voice is so intocxicating that you'd almost lost track of time. However, the root of her singing is always taking firm and deep in the ground. Just like a tree having weathered winds and rains and sunshine for ages, its green leaves fresh and strong, blossomes so lovely and its branches loaded down by fruits so lustrous. At times the tree would be a spirit who brings a mellow light into the forest and fills our hearts with joy and peace of mind.
Apparently with her past records, the voice of Cho Gong Rae allowed us to taste the joy of life. Her fascinating singing voice was already introduced to the audience overseas with the album "Chants rituels del'ile de Chindo"(VDE CD756). But there has nver been an album like this, which grasps her personality and her singing itself so straightforward. The fact that she's from Chindo, which has very distinctive nature of entertainment, perhaps ernders some background to create the core of her singing to a certain extent; but at the same time it cannot be that is the only aspent to raise her to what she is today. Such refreshing, still very much of earthbound, wherelse could we find a singer like this ? Neither only of Chindo, nor only of South Korean, it must be said that her song is a gem for all human being. Her beautiful voice melts all lust and greed of te world, streams through to purify our body and soul, There will always be a clear blue sky whenever and wherever Cho Gong Rae sings.
Manabu Yuasa - January 1995
조공례 - 방아타령
출처 :찻잔속에 달이뜨네
CHO GONG RAE - Linernotes
Cho Gong Rae is a celestial nymph, down on the grassland to sing her song. Her singing is a gentle, beautiful breeze, clear and vivid. Her singing voice creates a cool, refreshing steam in the air. Her everclear high note is filled with light but righ vitality, just like the chirping of the birds and brand new buds coming out in the early spring.
The voice of Cho Gong Rae has some kind of wildness in it, but It is not in the vein of any obvious primitive sensibility. It is something that one could feel the warmth and grace of wild nature. Her graceful, smooth voice is so intocxicating that you'd almost lost track of time. However, the root of her singing is always taking firm and deep in the ground. Just like a tree having weathered winds and rains and sunshine for ages, its green leaves fresh and strong, blossomes so lovely and its branches loaded down by fruits so lustrous. At times the tree would be a spirit who brings a mellow light into the forest and fills our hearts with joy and peace of mind.
Apparently with her past records, the voice of Cho Gong Rae allowed us to taste the joy of life. Her fascinating singing voice was already introduced to the audience overseas with the album "Chants rituels del'ile de Chindo"(VDE CD756). But there has nver been an album like this, which grasps her personality and her singing itself so straightforward. The fact that she's from Chindo, which has very distinctive nature of entertainment, perhaps ernders some background to create the core of her singing to a certain extent; but at the same time it cannot be that is the only aspent to raise her to what she is today. Such refreshing, still very much of earthbound, wherelse could we find a singer like this ? Neither only of Chindo, nor only of South Korean, it must be said that her song is a gem for all human being. Her beautiful voice melts all lust and greed of te world, streams through to purify our body and soul, There will always be a clear blue sky whenever and wherever Cho Gong Rae sings.
Manabu Yuasa - January 1995
조공례 - 방아타령
출처 :찻잔속에 달이뜨네
2010년 4월 8일 목요일
Atmel AVR coding with eclipse + winAVR
- Install AVR Plugin in Eclipse
Under "Avaiable Software", Click "Add Site.."
Insert the addressl; "http://avr-eclipse.sourceforge.net/updatesite/ "
Select "AVR Eclipse Plugin" and Install it.
- Install WinAVR
- Configuration it
2010년 4월 7일 수요일
In ADC2USB, CY7C68013's description
;;-----------------------------------------------------------------------------
;; File: dscr.a51
;; Contents: This file contains descriptor data tables.
;;
;; Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
;;-----------------------------------------------------------------------------
DSCR_DEVICE equ 1 ;; Descriptor type: Device
DSCR_CONFIG equ 2 ;; Descriptor type: Configuration
DSCR_STRING equ 3 ;; Descriptor type: String
DSCR_INTRFC equ 4 ;; Descriptor type: Interface
DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint
DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier
DSCR_DEVICE_LEN equ 18
DSCR_CONFIG_LEN equ 9
DSCR_INTRFC_LEN equ 9
DSCR_ENDPNT_LEN equ 7
DSCR_DEVQUAL_LEN equ 10
ET_CONTROL equ 0 ;; Endpoint type: Control
ET_ISO equ 1 ;; Endpoint type: Isochronous
ET_BULK equ 2 ;; Endpoint type: Bulk
ET_INT equ 3 ;; Endpoint type: Interrupt
;; iso bit2, 3
ISO_NOSYNC equ 00H
ISO_ASYNC equ 04H
ISO_ADAPTIVE equ 08H
ISO_SYNC equ 0CH
public DeviceDscr, DeviceQualDscr, HighSpeedConfigDscr, FullSpeedConfigDscr, StringDscr, UserDscr
;DSCR SEGMENT CODE
;;-----------------------------------------------------------------------------
;; Global Variables
;;-----------------------------------------------------------------------------
; rseg DSCR ;; locate the descriptor table in on-part memory.
CSEG AT 100H
DeviceDscr:
db DSCR_DEVICE_LEN ;; Descriptor length
db DSCR_DEVICE ;; Decriptor type
dw 0002H ;; Specification Version (BCD)
db 00H ;; Device class
db 00H ;; Device sub-class
db 00H ;; Device sub-sub-class
db 64 ;; Maximum packet size
dw 8304H ;; Vendor ID
dw 5057H ;; Product ID (Sample Device)
dw 0000H ;; Product version ID
db 1 ;; Manufacturer string index
db 2 ;; Product string index
db 0 ;; Serial number string index
db 1 ;; Number of configurations
org (($ / 2) +1) * 2
DeviceQualDscr:
db DSCR_DEVQUAL_LEN ;; Descriptor length
db DSCR_DEVQUAL ;; Decriptor type
dw 0002H ;; Specification Version (BCD)
db 00H ;; Device class
db 00H ;; Device sub-class
db 00H ;; Device sub-sub-class
db 64 ;; Maximum packet size
db 1 ;; Number of configurations
db 0 ;; Reserved
org (($ / 2) +1) * 2
HighSpeedConfigDscr:
db DSCR_CONFIG_LEN ;; Descriptor length
db DSCR_CONFIG ;; Descriptor type
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB)
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB)
db 1 ;; Number of interfaces
db 1 ;; Configuration number
db 0 ;; Configuration string
db 10100000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
db 50 ;; Power requirement (div 2 ma)
;; Alt Interface 0 Descriptor - Bulk IN
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 0 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_BULK ;; Endpoint type
db 00H ;; Maximun packet size (LSB)
db 02H ;; Max packect size (MSB) 512 byte packets/uFrame
db 00H ;; Polling interval
;; Alt. Interface 1 Descriptor - Isoc IN 3x1024 byte packets/uFrame
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 1 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index. This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Isoc IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_ISO ;; Endpoint type
;; db 20H ;; Maximum packet size (LSB)
;; db 0bH ;; Max packect size (MSB) 1011b 2*800 byte packets/uFrame
;; db 20H ;; Maximum packet size (LSB)
;; db 13H ;; Max packect size (MSB) 10011b 3*800 byte packets/uFrame
;; db 00H ;; Maximun packet size (LSB)
;; db 0cH ;; Max packect size (MSB) 01100b 2x1024 byte packets/uFrame
db 00H ;; Maximun packet size (LSB)
db 14H ;; Max packect size (MSB) 10100b 3x1024 byte packets/uFrame
db 01H ;; Polling interval
;; Alt. Interface 2 Descriptor - Isoc IN 1x1024 byte packets/uFrame
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 2 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index. This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Isoc IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_ISO ;; Endpoint type
;; db 20H ;; Maximun packet size (LSB)
;; db 03H ;; Max packect size (MSB) 00011b 800 byte packets/uFrame
db 00H ;; Maximun packet size (LSB)
db 04H ;; Max packect size (MSB) 00100b 1x1024 byte packets/uFrame
db 01H ;; Polling interval
HighSpeedConfigDscrEnd:
org (($ / 2) +1) * 2
FullSpeedConfigDscr:
db DSCR_CONFIG_LEN ;; Descriptor length
db DSCR_CONFIG ;; Descriptor type
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) mod 256 ;; Total Length (LSB)
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) / 256 ;; Total Length (MSB)
db 1 ;; Number of interfaces
db 1 ;; Configuration number
db 0 ;; Configuration string
db 10100000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
db 50 ;; Power requirement (div 2 ma)
;; Alt. Interface 0 Descriptor - Bulk IN
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 0 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint number, and direction
db ET_BULK ;; Endpoint type
db 040H ;; Maximun packet size (LSB)
db 00H ;; Max packect size (MSB)
db 01H ;; Polling interval
;; Alt. Interface 1 Descriptor - ISO IN
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 1 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index. This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Isoc IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint number, and direction
db ET_ISO ;; Endpoint type
db 0FFH ;; Maximun packet size (LSB)
db 03H ;; Max packect size (MSB) 1023 byte packets/Frame
db 01H ;; Polling interval
FullSpeedConfigDscrEnd:
org (($ / 2) +1) * 2
StringDscr:
StringDscr0:
db StringDscr0End-StringDscr0 ;; String descriptor length
db DSCR_STRING
db 09H,04H
StringDscr0End:
StringDscr1:
db StringDscr1End-StringDscr1 ;; String descriptor length
db DSCR_STRING
db 'D',00
db 'a',00
db 'y',00
db 's',00
db 'l',00
db 'e',00
db 'e',00
db 'p',00
StringDscr1End:
StringDscr2:
db StringDscr2End-StringDscr2 ;; Descriptor length
db DSCR_STRING
db 'A',00
db 'D',00
db 'C',00
db '2',00
db 'U',00
db 'S',00
db 'B',00
StringDscr2End:
/*
StringDscr3:
db StringDscr3End-StringDscr3 ;; Descriptor length
db DSCR_STRING
db 'B',00
db 'u',00
db 'l',00
db 'k',00
db '-',00
db 'I',00
db 'N',00
StringDscr3End:
*/
UserDscr:
dw 0000H
end
;; File: dscr.a51
;; Contents: This file contains descriptor data tables.
;;
;; Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
;;-----------------------------------------------------------------------------
DSCR_DEVICE equ 1 ;; Descriptor type: Device
DSCR_CONFIG equ 2 ;; Descriptor type: Configuration
DSCR_STRING equ 3 ;; Descriptor type: String
DSCR_INTRFC equ 4 ;; Descriptor type: Interface
DSCR_ENDPNT equ 5 ;; Descriptor type: Endpoint
DSCR_DEVQUAL equ 6 ;; Descriptor type: Device Qualifier
DSCR_DEVICE_LEN equ 18
DSCR_CONFIG_LEN equ 9
DSCR_INTRFC_LEN equ 9
DSCR_ENDPNT_LEN equ 7
DSCR_DEVQUAL_LEN equ 10
ET_CONTROL equ 0 ;; Endpoint type: Control
ET_ISO equ 1 ;; Endpoint type: Isochronous
ET_BULK equ 2 ;; Endpoint type: Bulk
ET_INT equ 3 ;; Endpoint type: Interrupt
;; iso bit2, 3
ISO_NOSYNC equ 00H
ISO_ASYNC equ 04H
ISO_ADAPTIVE equ 08H
ISO_SYNC equ 0CH
public DeviceDscr, DeviceQualDscr, HighSpeedConfigDscr, FullSpeedConfigDscr, StringDscr, UserDscr
;DSCR SEGMENT CODE
;;-----------------------------------------------------------------------------
;; Global Variables
;;-----------------------------------------------------------------------------
; rseg DSCR ;; locate the descriptor table in on-part memory.
CSEG AT 100H
DeviceDscr:
db DSCR_DEVICE_LEN ;; Descriptor length
db DSCR_DEVICE ;; Decriptor type
dw 0002H ;; Specification Version (BCD)
db 00H ;; Device class
db 00H ;; Device sub-class
db 00H ;; Device sub-sub-class
db 64 ;; Maximum packet size
dw 8304H ;; Vendor ID
dw 5057H ;; Product ID (Sample Device)
dw 0000H ;; Product version ID
db 1 ;; Manufacturer string index
db 2 ;; Product string index
db 0 ;; Serial number string index
db 1 ;; Number of configurations
org (($ / 2) +1) * 2
DeviceQualDscr:
db DSCR_DEVQUAL_LEN ;; Descriptor length
db DSCR_DEVQUAL ;; Decriptor type
dw 0002H ;; Specification Version (BCD)
db 00H ;; Device class
db 00H ;; Device sub-class
db 00H ;; Device sub-sub-class
db 64 ;; Maximum packet size
db 1 ;; Number of configurations
db 0 ;; Reserved
org (($ / 2) +1) * 2
HighSpeedConfigDscr:
db DSCR_CONFIG_LEN ;; Descriptor length
db DSCR_CONFIG ;; Descriptor type
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) mod 256 ;; Total Length (LSB)
db (HighSpeedConfigDscrEnd-HighSpeedConfigDscr) / 256 ;; Total Length (MSB)
db 1 ;; Number of interfaces
db 1 ;; Configuration number
db 0 ;; Configuration string
db 10100000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
db 50 ;; Power requirement (div 2 ma)
;; Alt Interface 0 Descriptor - Bulk IN
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 0 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_BULK ;; Endpoint type
db 00H ;; Maximun packet size (LSB)
db 02H ;; Max packect size (MSB) 512 byte packets/uFrame
db 00H ;; Polling interval
;; Alt. Interface 1 Descriptor - Isoc IN 3x1024 byte packets/uFrame
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 1 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index. This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Isoc IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_ISO ;; Endpoint type
;; db 20H ;; Maximum packet size (LSB)
;; db 0bH ;; Max packect size (MSB) 1011b 2*800 byte packets/uFrame
;; db 20H ;; Maximum packet size (LSB)
;; db 13H ;; Max packect size (MSB) 10011b 3*800 byte packets/uFrame
;; db 00H ;; Maximun packet size (LSB)
;; db 0cH ;; Max packect size (MSB) 01100b 2x1024 byte packets/uFrame
db 00H ;; Maximun packet size (LSB)
db 14H ;; Max packect size (MSB) 10100b 3x1024 byte packets/uFrame
db 01H ;; Polling interval
;; Alt. Interface 2 Descriptor - Isoc IN 1x1024 byte packets/uFrame
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 2 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index. This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Isoc IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint 2 and direction IN
db ET_ISO ;; Endpoint type
;; db 20H ;; Maximun packet size (LSB)
;; db 03H ;; Max packect size (MSB) 00011b 800 byte packets/uFrame
db 00H ;; Maximun packet size (LSB)
db 04H ;; Max packect size (MSB) 00100b 1x1024 byte packets/uFrame
db 01H ;; Polling interval
HighSpeedConfigDscrEnd:
org (($ / 2) +1) * 2
FullSpeedConfigDscr:
db DSCR_CONFIG_LEN ;; Descriptor length
db DSCR_CONFIG ;; Descriptor type
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) mod 256 ;; Total Length (LSB)
db (FullSpeedConfigDscrEnd-FullSpeedConfigDscr) / 256 ;; Total Length (MSB)
db 1 ;; Number of interfaces
db 1 ;; Configuration number
db 0 ;; Configuration string
db 10100000b ;; Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
db 50 ;; Power requirement (div 2 ma)
;; Alt. Interface 0 Descriptor - Bulk IN
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 0 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint number, and direction
db ET_BULK ;; Endpoint type
db 040H ;; Maximun packet size (LSB)
db 00H ;; Max packect size (MSB)
db 01H ;; Polling interval
;; Alt. Interface 1 Descriptor - ISO IN
db DSCR_INTRFC_LEN ;; Descriptor length
db DSCR_INTRFC ;; Descriptor type
db 0 ;; Zero-based index of this interface
db 1 ;; Alternate setting
db 3 ;; Number of end points
db 0ffH ;; Interface class
db 00H ;; Interface sub class
db 00H ;; Interface sub sub class
db 0 ;; Interface descriptor string index. This would be nice to add!
;; Bulk IN Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 81H
db ET_BULK
db 40H
db 00H
db 00H
;; Bulk OUT Endpoint Descriptor (EP1)
db DSCR_ENDPNT_LEN
db DSCR_ENDPNT
db 01H
db ET_BULK
db 40H
db 00H
db 00H
;; Isoc IN Endpoint Descriptor (EP2)
db DSCR_ENDPNT_LEN ;; Descriptor length
db DSCR_ENDPNT ;; Descriptor type
db 82H ;; Endpoint number, and direction
db ET_ISO ;; Endpoint type
db 0FFH ;; Maximun packet size (LSB)
db 03H ;; Max packect size (MSB) 1023 byte packets/Frame
db 01H ;; Polling interval
FullSpeedConfigDscrEnd:
org (($ / 2) +1) * 2
StringDscr:
StringDscr0:
db StringDscr0End-StringDscr0 ;; String descriptor length
db DSCR_STRING
db 09H,04H
StringDscr0End:
StringDscr1:
db StringDscr1End-StringDscr1 ;; String descriptor length
db DSCR_STRING
db 'D',00
db 'a',00
db 'y',00
db 's',00
db 'l',00
db 'e',00
db 'e',00
db 'p',00
StringDscr1End:
StringDscr2:
db StringDscr2End-StringDscr2 ;; Descriptor length
db DSCR_STRING
db 'A',00
db 'D',00
db 'C',00
db '2',00
db 'U',00
db 'S',00
db 'B',00
StringDscr2End:
/*
StringDscr3:
db StringDscr3End-StringDscr3 ;; Descriptor length
db DSCR_STRING
db 'B',00
db 'u',00
db 'l',00
db 'k',00
db '-',00
db 'I',00
db 'N',00
StringDscr3End:
*/
UserDscr:
dw 0000H
end
In ADC2USB, CY7C68013's C-code
#pragma NOIV // Do not generate interrupt vectors
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
#include "binary.h"
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
enum {
Alt0_BulkIN = 0,
Alt1_IsocTripleIN,
Alt2_IsocIN
};
enum {
Full_Alt0_BulkIN = 0,
Full_Alt1_IsocIN
};
BYTE Configuration; // Current configuration
BYTE AlternateSetting = Alt0_BulkIN; // Alternate settings
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// int i,j;
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1 | bmCLKOE);
SYNCDELAY;
// when IFCFG[1:0] = 0b11,
// FIFOADR[1:0], PKTEND, and SLOE are automatically configured
// for PORTA
// PA.3(PORTACFG.3=0, WU2EN=0)
// PA.2(PORTACFG.2=0)
// PA.1(PORTACFG.1=0)
// PA.0(PORTACFG.0=0)
PORTACFG = 0;
WAKEUPCS &= ~0x02; // WU2EN=0
OEA = 0x08b; // Input FIFOADR[0:1], PKTEND, OUTPUT(PA0, PA1)
IOA = 0;
PA0 = 0;
PA1 = 0;
// When IFCFG.1 = 1
// PB[0:7] is configured as FD[0:7]
OEB = 0; // Input as FD[0:7]
IOB = 0;
// When IFCFG.1 = 1 and any WORDWIDE bit = 1
// PD[0:7] is configured as FD[8:15]
OED = 0; // Input as FD[8:15]
IOD = 0;
PORTECFG = 0x03; // needs to be set GSTATE to zero
OEE = 0x3; // IFCLK, CLKOUT
IOE = 0;
/* 1. Configure bits IFCONFIG[7:4] to define the behavior of the interface clock. */
// IFCONFIG
// bit7 : IFCLKSRC(0 -> exernal clock, 1 -> internal clock)
// bit6 : 3048MHZ(0 -> 30Mhz, 1 -> 48Mhz)
// bit5 : IFCLKOE(0 -> disable, 1-> enable internal clock output)
// bit4 : IFCLKPOL(invert external or internal clock)
// bit3 : ASYNC(0 -> synchronous, 1 -> asynchronous)
// bit2 : GSTATE(0 -> disable GSTATE, 1-> enable GSTATE)
// bit1 : IFCFG[1:0] (0b00: ports, 0b01: reserved, 0b10: GPIF, 0b11: Slave fifo)
// bit0 :
IFCONFIG = b01010100; // ext, 48Mhz, disable OE, invert, synchronous, enable GSTATE, ports
/* 2. Set bits IFCFG1:0=11. */
IFCONFIG |= b00000011;
SYNCDELAY;
/* 3. Set REVCTL.0 and REVCTL.1 to 1. */
REVCTL = 0x03;
SYNCDELAY;
/* 4. Configure EPxCFG. */
// Default interface uses endpoint 2, zero the valid bit on all others
// Just using endpoint 2, zero the valid bit on all others
EP1OUTCFG = 0xA0; //bmVALID | bmBULK;
SYNCDELAY;
EP1INCFG = 0xA0; //bmVALID | bmBULK;
SYNCDELAY;
// EPxCFG
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; //EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
EP4CFG = (EP4CFG & 0x7F); //non-valid
SYNCDELAY;
EP6CFG = (EP6CFG & 0x7F); //non-valid
SYNCDELAY;
EP8CFG = (EP8CFG & 0x7F); //non-valid
SYNCDELAY;
// EPxFIFOCFG
// bit7 : reserved
// bit6 : INFM1(IN Full Minus One)
// bit5 : OEP2(OUT Empty Plus One)
// bit4 : AUTOOUT
// bit3 : AUTOIN
// bit2 : ZEROLENIN(Enable Zero-length IN Packets)
// bit1 : reserved
// bit0 : WORDWIDE(Select Byte/Word FIFOs on PORTB/D Pins)
//EP2FIFOCFG = 0x01;
EP2FIFOCFG = 0x00; // 8bit FD
SYNCDELAY;
EP4FIFOCFG = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x00;
SYNCDELAY;
EP8FIFOCFG = 0x00;
SYNCDELAY;
/* 5. Reset the FIFOs. */
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY; //
/* 6. Set bit EPxFIFOCFG.3=1. */
EP2FIFOCFG |= 0x08; // AUTOIN
/* 7. Set the size via the EPxAUTOINLENH:L registers. */
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
// We want to get SOF interrupts
USBIE |= bmSOF;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
if (PA0) PA0 = 0; // de-assert reset
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
BYTE updateDisplay = TRUE;
AlternateSetting = SETUPDAT[2];
// ...FX2 in high speed mode
if (EZUSB_HIGHSPEED()) {
// Change configuration based upon the Alt. Interface selected
switch (AlternateSetting) {
case Alt0_BulkIN:
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
break;
case Alt1_IsocTripleIN:
// Only using endpoint 2, zero the valid bit on all others
EP2CFG = 0xD8; //bmVALID | bmIN | bmISOC | bm1024 | bmQUAD // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1024);
SYNCDELAY;
EP2AUTOINLENL = LSB(1024);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x03;
break;
case Alt2_IsocIN:
EP2CFG = 0xD8; //bmVALID | bmIN | bmISOC | bm1024 | bmQUAD // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1024);
SYNCDELAY;
EP2AUTOINLENL = LSB(1024);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
break;
}
} else {
// Change configuration based upon the Alt. Interface selected
switch (AlternateSetting) {
case Full_Alt0_BulkIN:
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
break;
case Full_Alt1_IsocIN:
EP2CFG = 0xD8; // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1023);
SYNCDELAY;
EP2AUTOINLENL = LSB(1023);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
break;
}
}
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
#include "commands.h"
#define bRequestType SETUPDAT[0]
#define bRequest SETUPDAT[1]
#define wValueL SETUPDAT[2]
#define wValueH SETUPDAT[3]
#define wIndexL SETUPDAT[4]
#define wIndexH SETUPDAT[5]
#define wLengthL SETUPDAT[6]
#define wLengthH SETUPDAT[7]
BOOL DR_VendorCmnd(void)
{
// BYTE xdata tmp[2];
switch (bRequest) {
case VRQ_GET_STATUS:
EP0BUF[0] = IFCONFIG;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
case VRQ_SEND_RESET: PA0 = 1; break;
case VRQ_I2C_WRITE:
// tmp[0] = wIndexL; tmp[1] = wValueL;
// if (EZUSB_WriteI2C(CAM_I2C_ID, 2, &(tmp[0])) != I2C_OK) return TRUE;
break;
case VRQ_I2C_READ:
//IOA ^= 0x04;
//tmp[0] = wIndexL; //i2c_id;
// if (EZUSB_WriteI2C(CAM_I2C_ID, 1, &wIndexL) != I2C_OK) return TRUE;
// EZUSB_WaitForEEPROMWrite(CAM_I2C_ID);
// if (EZUSB_ReadI2C(CAM_I2C_ID, 1, EP1INBUF) != I2C_OK) return TRUE;
//EP1INBUF[0] = tmp[0]; SYNCDELAY;
// EP1INBC = 1; SYNCDELAY; // arm EP6IN
/*
// echo
EP0BUF[0] = tmp[0];
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
*/
break;
#if 0
// case VRQ_SEND_GRAB: PA0 = 0; TR0 = 1; break;
// case VRQ_SEND_START: PA0 = 0; break;
// case VRQ_SEND_STOP: PA0 = 1; break;
case VRQ_SET_CAM:
// if (system_status == NORMAL_STATUS) system_status = SLFIFO_INIT;
// else SEND_START();
break;
case VRQ_RESET_CAM:
// if (system_status != NORMAL_STATUS) system_status = NORMAL_INIT;
break;
#endif
default: return TRUE;
}
return FALSE;
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures(void) interrupt 0
{
if (EZUSB_HIGHSPEED()) {
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
} else {
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp(void) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUSP;
}
void ISR_Highspeed(void) interrupt 0
{
if (EZUSB_HIGHSPEED()) {
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x03;
} else {
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
// ISR_Ep2inout is called on every OUT packet receieved.
// We don't do anything with the data. We just indicate we are done with the buffer.
void ISR_Ep2inout(void) interrupt 0
{
// Perform USB activity based upon the Alt. Interface selected
/*
switch (AlternateSetting)
{
case Alt1_BulkOUT:
case Alt4_IsocOUT:
// check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP2EMPTY))
{
EP2BCL = 0x80; // re(arm) EP2OUT
}
break;
case Alt2_BulkINOUT:
case Alt6_IsocINOUT:
// check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP6EMPTY))
{
EP6BCL = 0x80; // re(arm) EP6OUT
}
break;
}
*/
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro
#include "binary.h"
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
enum {
Alt0_BulkIN = 0,
Alt1_IsocTripleIN,
Alt2_IsocIN
};
enum {
Full_Alt0_BulkIN = 0,
Full_Alt1_IsocIN
};
BYTE Configuration; // Current configuration
BYTE AlternateSetting = Alt0_BulkIN; // Alternate settings
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
void TD_Init(void) // Called once at startup
{
// int i,j;
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1 | bmCLKOE);
SYNCDELAY;
// when IFCFG[1:0] = 0b11,
// FIFOADR[1:0], PKTEND, and SLOE are automatically configured
// for PORTA
// PA.3(PORTACFG.3=0, WU2EN=0)
// PA.2(PORTACFG.2=0)
// PA.1(PORTACFG.1=0)
// PA.0(PORTACFG.0=0)
PORTACFG = 0;
WAKEUPCS &= ~0x02; // WU2EN=0
OEA = 0x08b; // Input FIFOADR[0:1], PKTEND, OUTPUT(PA0, PA1)
IOA = 0;
PA0 = 0;
PA1 = 0;
// When IFCFG.1 = 1
// PB[0:7] is configured as FD[0:7]
OEB = 0; // Input as FD[0:7]
IOB = 0;
// When IFCFG.1 = 1 and any WORDWIDE bit = 1
// PD[0:7] is configured as FD[8:15]
OED = 0; // Input as FD[8:15]
IOD = 0;
PORTECFG = 0x03; // needs to be set GSTATE to zero
OEE = 0x3; // IFCLK, CLKOUT
IOE = 0;
/* 1. Configure bits IFCONFIG[7:4] to define the behavior of the interface clock. */
// IFCONFIG
// bit7 : IFCLKSRC(0 -> exernal clock, 1 -> internal clock)
// bit6 : 3048MHZ(0 -> 30Mhz, 1 -> 48Mhz)
// bit5 : IFCLKOE(0 -> disable, 1-> enable internal clock output)
// bit4 : IFCLKPOL(invert external or internal clock)
// bit3 : ASYNC(0 -> synchronous, 1 -> asynchronous)
// bit2 : GSTATE(0 -> disable GSTATE, 1-> enable GSTATE)
// bit1 : IFCFG[1:0] (0b00: ports, 0b01: reserved, 0b10: GPIF, 0b11: Slave fifo)
// bit0 :
IFCONFIG = b01010100; // ext, 48Mhz, disable OE, invert, synchronous, enable GSTATE, ports
/* 2. Set bits IFCFG1:0=11. */
IFCONFIG |= b00000011;
SYNCDELAY;
/* 3. Set REVCTL.0 and REVCTL.1 to 1. */
REVCTL = 0x03;
SYNCDELAY;
/* 4. Configure EPxCFG. */
// Default interface uses endpoint 2, zero the valid bit on all others
// Just using endpoint 2, zero the valid bit on all others
EP1OUTCFG = 0xA0; //bmVALID | bmBULK;
SYNCDELAY;
EP1INCFG = 0xA0; //bmVALID | bmBULK;
SYNCDELAY;
// EPxCFG
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; //EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
EP4CFG = (EP4CFG & 0x7F); //non-valid
SYNCDELAY;
EP6CFG = (EP6CFG & 0x7F); //non-valid
SYNCDELAY;
EP8CFG = (EP8CFG & 0x7F); //non-valid
SYNCDELAY;
// EPxFIFOCFG
// bit7 : reserved
// bit6 : INFM1(IN Full Minus One)
// bit5 : OEP2(OUT Empty Plus One)
// bit4 : AUTOOUT
// bit3 : AUTOIN
// bit2 : ZEROLENIN(Enable Zero-length IN Packets)
// bit1 : reserved
// bit0 : WORDWIDE(Select Byte/Word FIFOs on PORTB/D Pins)
//EP2FIFOCFG = 0x01;
EP2FIFOCFG = 0x00; // 8bit FD
SYNCDELAY;
EP4FIFOCFG = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x00;
SYNCDELAY;
EP8FIFOCFG = 0x00;
SYNCDELAY;
/* 5. Reset the FIFOs. */
FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
SYNCDELAY; //
FIFORESET = 0x02; // reset, FIFO 2
SYNCDELAY; //
FIFORESET = 0x00; // deactivate NAK-ALL
SYNCDELAY; //
/* 6. Set bit EPxFIFOCFG.3=1. */
EP2FIFOCFG |= 0x08; // AUTOIN
/* 7. Set the size via the EPxAUTOINLENH:L registers. */
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
// We want to get SOF interrupts
USBIE |= bmSOF;
}
void TD_Poll(void) // Called repeatedly while the device is idle
{
if (PA0) PA0 = 0; // de-assert reset
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
BYTE updateDisplay = TRUE;
AlternateSetting = SETUPDAT[2];
// ...FX2 in high speed mode
if (EZUSB_HIGHSPEED()) {
// Change configuration based upon the Alt. Interface selected
switch (AlternateSetting) {
case Alt0_BulkIN:
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
break;
case Alt1_IsocTripleIN:
// Only using endpoint 2, zero the valid bit on all others
EP2CFG = 0xD8; //bmVALID | bmIN | bmISOC | bm1024 | bmQUAD // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1024);
SYNCDELAY;
EP2AUTOINLENL = LSB(1024);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x03;
break;
case Alt2_IsocIN:
EP2CFG = 0xD8; //bmVALID | bmIN | bmISOC | bm1024 | bmQUAD // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1024);
SYNCDELAY;
EP2AUTOINLENL = LSB(1024);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
break;
}
} else {
// Change configuration based upon the Alt. Interface selected
switch (AlternateSetting) {
case Full_Alt0_BulkIN:
EP2CFG = 0xE0; //bmVALID | bmIN | bmBULK; // EP2 is DIR=IN, TYPE=BULK, SIZE=512, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(512);
SYNCDELAY;
EP2AUTOINLENL = LSB(512);
SYNCDELAY;
// Reset data toggle to 0
TOGCTL = 0x12; // EP2 IN
TOGCTL = 0x32; // EP2 IN Reset
break;
case Full_Alt1_IsocIN:
EP2CFG = 0xD8; // EP2 is DIR=IN, TYPE=ISOC, SIZE=1024, BUF=4x
SYNCDELAY;
// Clear out any committed packets
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x02;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
// this is the length for high speed
EP2AUTOINLENH = MSB(1023);
SYNCDELAY;
EP2AUTOINLENL = LSB(1023);
SYNCDELAY;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x01;
break;
}
}
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
#include "commands.h"
#define bRequestType SETUPDAT[0]
#define bRequest SETUPDAT[1]
#define wValueL SETUPDAT[2]
#define wValueH SETUPDAT[3]
#define wIndexL SETUPDAT[4]
#define wIndexH SETUPDAT[5]
#define wLengthL SETUPDAT[6]
#define wLengthH SETUPDAT[7]
BOOL DR_VendorCmnd(void)
{
// BYTE xdata tmp[2];
switch (bRequest) {
case VRQ_GET_STATUS:
EP0BUF[0] = IFCONFIG;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
case VRQ_SEND_RESET: PA0 = 1; break;
case VRQ_I2C_WRITE:
// tmp[0] = wIndexL; tmp[1] = wValueL;
// if (EZUSB_WriteI2C(CAM_I2C_ID, 2, &(tmp[0])) != I2C_OK) return TRUE;
break;
case VRQ_I2C_READ:
//IOA ^= 0x04;
//tmp[0] = wIndexL; //i2c_id;
// if (EZUSB_WriteI2C(CAM_I2C_ID, 1, &wIndexL) != I2C_OK) return TRUE;
// EZUSB_WaitForEEPROMWrite(CAM_I2C_ID);
// if (EZUSB_ReadI2C(CAM_I2C_ID, 1, EP1INBUF) != I2C_OK) return TRUE;
//EP1INBUF[0] = tmp[0]; SYNCDELAY;
// EP1INBC = 1; SYNCDELAY; // arm EP6IN
/*
// echo
EP0BUF[0] = tmp[0];
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
*/
break;
#if 0
// case VRQ_SEND_GRAB: PA0 = 0; TR0 = 1; break;
// case VRQ_SEND_START: PA0 = 0; break;
// case VRQ_SEND_STOP: PA0 = 1; break;
case VRQ_SET_CAM:
// if (system_status == NORMAL_STATUS) system_status = SLFIFO_INIT;
// else SEND_START();
break;
case VRQ_RESET_CAM:
// if (system_status != NORMAL_STATUS) system_status = NORMAL_INIT;
break;
#endif
default: return TRUE;
}
return FALSE;
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures(void) interrupt 0
{
if (EZUSB_HIGHSPEED()) {
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
} else {
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp(void) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUSP;
}
void ISR_Highspeed(void) interrupt 0
{
if (EZUSB_HIGHSPEED()) {
pConfigDscr = pHighSpeedConfigDscr;
pOtherConfigDscr = pFullSpeedConfigDscr;
// This register sets the number of Isoc packets to send per
// uFrame. This register is only valid in high speed.
EP2ISOINPKTS = 0x03;
} else {
pConfigDscr = pFullSpeedConfigDscr;
pOtherConfigDscr = pHighSpeedConfigDscr;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
// ISR_Ep2inout is called on every OUT packet receieved.
// We don't do anything with the data. We just indicate we are done with the buffer.
void ISR_Ep2inout(void) interrupt 0
{
// Perform USB activity based upon the Alt. Interface selected
/*
switch (AlternateSetting)
{
case Alt1_BulkOUT:
case Alt4_IsocOUT:
// check EP2 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP2EMPTY))
{
EP2BCL = 0x80; // re(arm) EP2OUT
}
break;
case Alt2_BulkINOUT:
case Alt6_IsocINOUT:
// check EP6 EMPTY(busy) bit in EP2468STAT (SFR), core set's this bit when FIFO is empty
if(!(EP2468STAT & bmEP6EMPTY))
{
EP6BCL = 0x80; // re(arm) EP6OUT
}
break;
}
*/
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
ADC2USB Verilog HDL
External - CPLD : Reset, Clk, Trigger, LED
CY7C68013 - CPLD : nSLWR, FD
AD7829 - CPLD : nCONVST, nEOC, A, nRD, DB
// 20Mhz OSC
// 19.53126 khz sampling
// sampling count 10bits
module adc2usb(Reset, Clk, Trigger, LED,
nCONVST, nEOC, A, /*nCS,*/ nRD, DB,
/*Ifclk,*/ /*nFlagB,*/ /*nPKTEND,*/ nSLWR, FD,);
input wire Reset;
input wire Clk;
input [7:0] Trigger;
output wire [4:0] LED;
/* interface to ADC (AD7829) */
output reg nCONVST;
input wire nEOC;
output wire [2:0] A;
//output reg [2:0] A;
//output reg nCS;
output reg nRD;
input [7:0] DB;
/* interface to USB FIFO (CY7C68013A) */
//output Ifclk;
//input wire nFlagB;
//output reg nPKTEND;
output reg nSLWR;
output reg [7:0] FD;
// FSM for adc
parameter STATE_BITS = 7;
parameter IDLE = 7'b0000001;
parameter SAVE_TRIGGER = 7'b0000010;
parameter TX_TRIGGER = 7'b0000100;
parameter START_ADC = 7'b0001000;
parameter WAIT_EOC = 7'b0010000;
parameter RD_ADC_MUX_ADDR = 7'b0100000;
parameter TX_ADC = 7'b1000000;
function [STATE_BITS-1:0] adc2usb_fsm;
input [STATE_BITS-1:0] state;
input count_zero;
input channel_zero;
input sample_zero;
input start;
input endofconv;
case (state)
IDLE:
if (count_zero) begin
if (channel_zero) begin
if (sample_zero) begin
if (start) begin
adc2usb_fsm = SAVE_TRIGGER;
end else begin
adc2usb_fsm = IDLE;
end
end else begin
adc2usb_fsm = TX_TRIGGER;
end
end else begin
adc2usb_fsm = START_ADC;
end
end else begin
adc2usb_fsm = IDLE;
end
SAVE_TRIGGER:
adc2usb_fsm = TX_TRIGGER;
TX_TRIGGER:
adc2usb_fsm = START_ADC;
START_ADC:
adc2usb_fsm = WAIT_EOC;
WAIT_EOC:
if (endofconv) adc2usb_fsm = WAIT_EOC;
else adc2usb_fsm = RD_ADC_MUX_ADDR;
RD_ADC_MUX_ADDR:
adc2usb_fsm = TX_ADC;
TX_ADC:
adc2usb_fsm = IDLE;
default:
adc2usb_fsm = IDLE;
endcase
endfunction
wire adc_start;
assign adc_start = |(Trigger);
assign LED[0] = |(Trigger);
reg [19:0] adc_count;
wire [9:0] sample_count;
assign sample_count = adc_count[19:10];
wire [2:0] channel_count;
assign channel_count = adc_count[9:7];
wire adc_started;
assign adc_started = |(adc_count);
assign LED[1] = |(adc_count);
wire sample_is_zero;
assign sample_is_zero = ~|(adc_count[19:10]);
assign LED[2] = ~|(adc_count[19:10]);
wire channel_is_zero;
assign channel_is_zero = ~|(adc_count[9:7]);
assign LED[3] = ~|(adc_count[9:7]);
wire other_is_zero;
assign other_is_zero = ~|(adc_count[6:0]);
assign LED[4] = ~|(adc_count[6:0]);
always @(posedge Clk) begin
// if (Reset) begin
// adc_count <= 0;
// end else begin
if (adc_started|adc_start) adc_count <= adc_count+1;
else adc_count <= 0;
// end
end
reg [STATE_BITS-1:0] state;
wire [STATE_BITS-1:0] next_state;
assign next_state = adc2usb_fsm(state, other_is_zero, channel_is_zero, sample_is_zero, adc_start, nEOC/* 1'b0 */);
always @(posedge Clk) begin
// if (Reset) begin
// state <= IDLE;
// end else begin
state <= next_state;
// end
end
assign A = channel_count+1;
//assign A = {~|(state^TX_ADC), ~|(state^WAIT_EOC), ~|(state^START_ADC)}; //adc_count[2:0];
always @(posedge Clk) begin
// if (Reset) begin
// nCONVST <= 1'b1;
// end else begin
if (~|(state^START_ADC)) nCONVST <= 1'b0;
else nCONVST <= 1'b1;
// end
end
always @(posedge Clk) begin
// if (Reset) begin
// nRD <= 1'b1;
// end else begin
if (~|(state^RD_ADC_MUX_ADDR)) nRD <= 1'b0;
else nRD <= 1'b1;
// end
end
reg [7:0] saved_trigger;
always @(posedge Clk) begin
if (~|(state^SAVE_TRIGGER)) saved_trigger = Trigger;
end
always @(posedge Clk) begin
if (~|(state^TX_TRIGGER)) FD <= saved_trigger;
else if (~|(state^TX_ADC)) FD <= DB;
end
always @(posedge Clk) begin
// if (Reset) begin
// nSLWR <= 1'b1;
// end else begin
if (~|(state^TX_TRIGGER)) nSLWR <= 1'b0;
else if ((~|(state^TX_ADC))&(saved_trigger[channel_count])) nSLWR <= 1'b0;
else nSLWR <= 1'b1;
// end
end
endmodule
CY7C68013 - CPLD : nSLWR, FD
AD7829 - CPLD : nCONVST, nEOC, A, nRD, DB
// 20Mhz OSC
// 19.53126 khz sampling
// sampling count 10bits
module adc2usb(Reset, Clk, Trigger, LED,
nCONVST, nEOC, A, /*nCS,*/ nRD, DB,
/*Ifclk,*/ /*nFlagB,*/ /*nPKTEND,*/ nSLWR, FD,);
input wire Reset;
input wire Clk;
input [7:0] Trigger;
output wire [4:0] LED;
/* interface to ADC (AD7829) */
output reg nCONVST;
input wire nEOC;
output wire [2:0] A;
//output reg [2:0] A;
//output reg nCS;
output reg nRD;
input [7:0] DB;
/* interface to USB FIFO (CY7C68013A) */
//output Ifclk;
//input wire nFlagB;
//output reg nPKTEND;
output reg nSLWR;
output reg [7:0] FD;
// FSM for adc
parameter STATE_BITS = 7;
parameter IDLE = 7'b0000001;
parameter SAVE_TRIGGER = 7'b0000010;
parameter TX_TRIGGER = 7'b0000100;
parameter START_ADC = 7'b0001000;
parameter WAIT_EOC = 7'b0010000;
parameter RD_ADC_MUX_ADDR = 7'b0100000;
parameter TX_ADC = 7'b1000000;
function [STATE_BITS-1:0] adc2usb_fsm;
input [STATE_BITS-1:0] state;
input count_zero;
input channel_zero;
input sample_zero;
input start;
input endofconv;
case (state)
IDLE:
if (count_zero) begin
if (channel_zero) begin
if (sample_zero) begin
if (start) begin
adc2usb_fsm = SAVE_TRIGGER;
end else begin
adc2usb_fsm = IDLE;
end
end else begin
adc2usb_fsm = TX_TRIGGER;
end
end else begin
adc2usb_fsm = START_ADC;
end
end else begin
adc2usb_fsm = IDLE;
end
SAVE_TRIGGER:
adc2usb_fsm = TX_TRIGGER;
TX_TRIGGER:
adc2usb_fsm = START_ADC;
START_ADC:
adc2usb_fsm = WAIT_EOC;
WAIT_EOC:
if (endofconv) adc2usb_fsm = WAIT_EOC;
else adc2usb_fsm = RD_ADC_MUX_ADDR;
RD_ADC_MUX_ADDR:
adc2usb_fsm = TX_ADC;
TX_ADC:
adc2usb_fsm = IDLE;
default:
adc2usb_fsm = IDLE;
endcase
endfunction
wire adc_start;
assign adc_start = |(Trigger);
assign LED[0] = |(Trigger);
reg [19:0] adc_count;
wire [9:0] sample_count;
assign sample_count = adc_count[19:10];
wire [2:0] channel_count;
assign channel_count = adc_count[9:7];
wire adc_started;
assign adc_started = |(adc_count);
assign LED[1] = |(adc_count);
wire sample_is_zero;
assign sample_is_zero = ~|(adc_count[19:10]);
assign LED[2] = ~|(adc_count[19:10]);
wire channel_is_zero;
assign channel_is_zero = ~|(adc_count[9:7]);
assign LED[3] = ~|(adc_count[9:7]);
wire other_is_zero;
assign other_is_zero = ~|(adc_count[6:0]);
assign LED[4] = ~|(adc_count[6:0]);
always @(posedge Clk) begin
// if (Reset) begin
// adc_count <= 0;
// end else begin
if (adc_started|adc_start) adc_count <= adc_count+1;
else adc_count <= 0;
// end
end
reg [STATE_BITS-1:0] state;
wire [STATE_BITS-1:0] next_state;
assign next_state = adc2usb_fsm(state, other_is_zero, channel_is_zero, sample_is_zero, adc_start, nEOC/* 1'b0 */);
always @(posedge Clk) begin
// if (Reset) begin
// state <= IDLE;
// end else begin
state <= next_state;
// end
end
assign A = channel_count+1;
//assign A = {~|(state^TX_ADC), ~|(state^WAIT_EOC), ~|(state^START_ADC)}; //adc_count[2:0];
always @(posedge Clk) begin
// if (Reset) begin
// nCONVST <= 1'b1;
// end else begin
if (~|(state^START_ADC)) nCONVST <= 1'b0;
else nCONVST <= 1'b1;
// end
end
always @(posedge Clk) begin
// if (Reset) begin
// nRD <= 1'b1;
// end else begin
if (~|(state^RD_ADC_MUX_ADDR)) nRD <= 1'b0;
else nRD <= 1'b1;
// end
end
reg [7:0] saved_trigger;
always @(posedge Clk) begin
if (~|(state^SAVE_TRIGGER)) saved_trigger = Trigger;
end
always @(posedge Clk) begin
if (~|(state^TX_TRIGGER)) FD <= saved_trigger;
else if (~|(state^TX_ADC)) FD <= DB;
end
always @(posedge Clk) begin
// if (Reset) begin
// nSLWR <= 1'b1;
// end else begin
if (~|(state^TX_TRIGGER)) nSLWR <= 1'b0;
else if ((~|(state^TX_ADC))&(saved_trigger[channel_count])) nSLWR <= 1'b0;
else nSLWR <= 1'b1;
// end
end
endmodule
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